1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to a semiconductor device capable of expanding an area of safe operating, avoiding thermal runaway, and achieving a reduction of resistance components, in a transistor.
2. Description of the Related Art
As a bipolar transistor of a discrete type, known is a bipolar transistor in which base electrodes are arranged in two layers and emitter electrodes are arranged in two layers, on an operating region formed of a lattice-patterned emitter region and an island-shaped base region (this technology is described for instance in Japanese Patent Application Publication No. 2000-40703).
With reference to FIG. 6, a conventional semiconductor device is described taking an npn type transistor as an example.
FIG. 6A is a plan view of an entire semiconductor device 100. FIG. 6B is a cross-sectional view taken along the line i-i of FIG. 6A. FIG. 6C is a cross-sectional view taken along the line j-j of FIG. 6A. In addition, electrodes of a second layer are shown in dashed lines in FIG. 6A.
On an n+ type silicon semiconductor substrate 51a, a collector region is provided, for example, by stacking an n− type semiconductor layer 51b or by other method. On a surface of the n− type semiconductor layer 51b, a base region 53, which is a p type impurity region, is provided. On a surface of the base region 53, an emitter region 54 is formed by diffusing n+ type impurities in a lattice pattern. Accordingly, the base region 53 is separated into islands, and the resultant islands are arranged alternately with portions of the emitter region 54. Here, the base region has its surface portion separated into islands, and a deep region which is formed below the emitter region 54 is continuous. A transistor including the base region thus divided into islands and the emitter region surrounding the islands is hereinafter referred to as a cell, and a region in which a number of cells are arranged is referred to as an operating region 58.
Base electrodes connected to the base region 53 are formed in a two-layer structure, and emitter electrodes connected to the emitter region 54 are formed in a two-layer structure. Base electrodes on a first layer consist of island-shaped first base electrodes 56a and strip-shaped first base electrodes 56b, and come into contact with the base region 53 through contact holes CH1′ provided in a first insulating film 61. The island-shaped first base electrodes 56a and the strip-shaped first base electrodes 56b are respectively arranged in regions halved at an almost center of the operating region 58.
First emitter electrodes 57 are provided in a lattice pattern, and each arranged between the first base electrodes 56a, or between the first base electrodes 56a, 56b. The first emitter electrodes 57 come into contact with the portions of the emitter region 54 through contact holes CH2′ provided in the first insulating film 61.
On the first base electrodes 56a, 56b and the first emitter electrodes 57, a second insulating film 62 is provided. On the second insulating film 62, a plate like second base electrode 66 and a second emitter electrode 67, which constitute a second layer, are further provided. The second base electrode 66 comes into contact with the island-shaped first base electrodes 56a and end portions of the strip-shaped first base electrodes 56b through through holes TH1′ provided in the second insulating film 62 (see FIG. 6A). The second emitter electrode 67 comes into contact with the first emitter electrodes 57 through through holes TH2′ provided in the second insulating film 62 (see FIG. 6B). The plate like second base electrode 66 and the second emitter electrode 67 are equivalent in area, and are each connected with bonding wires (not shown) made of gold (Au) or the like.